1. Field of the Invention
The present invention relates to a readout circuit used for reading out data stored in a memory cell of a nonvolatile semiconductor memory device.
2. Description of the Related Art
In Japanese Laid Open Patent Application JP-B-Heisei 02-049519, a readout circuit used for reading out data stored in a memory cell of a semiconductor memory device is disclosed. FIG. 1 is a circuit diagram showing a configuration of a nonvolatile semiconductor memory device to which the readout circuit mentioned above is applied. The nonvolatile semiconductor memory device 100 is provided with a memory cell 110 and a readout circuit 130 for sensing a data stored in the memory cell 110. The readout circuit 130 includes a dummy cell 120, a current sense amplifier circuit 140 and a reference current circuit 150.
The memory cell 110 is a stacked gate type N-channel transistor, and includes a control gate and a floating gate. The dummy cell 120 has almost the same structure as the memory cell 110. However, the control gate and the floating gate of the dummy cell 120 are shorted with each other. When electrons (e.g. hot electrons) are injected into the floating gate of the memory cell 110, a threshold voltage of the memory cell 110 is changed. The threshold voltage becomes higher when electrons are injected into the floating gate, while becomes lower when electrons are drawn out of the floating gate. The nonvolatile semiconductor memory device such as a flash memory stores data by utilizing such a change in characteristics.
With regard to the stacked gate type memory cell transistor, a drain current flows when a voltage higher than the threshold voltage is applied to the control gate. The state mentioned above is referred to as an operation in a “strong inversion region”. The drain current Id of a general MOS transistor in the “strong inversion region” is expressed by the following equation:
                              I          d                =                              W            L                    ⁢          μ          ⁢                                          ⁢                                    C              ox                        ⁡                          [                                                                    (                                                                  V                        g                                            -                                              V                        t                                                              )                                    ⁢                                      V                    d                                                  -                                                      1                    2                                    ⁢                                      V                    d                    2                                                              ]                                                          (        1        )            
Here, Vg is a gate-source voltage (Vgs), Vd is a drain-source voltage (Vds), and Vt is the threshold voltage. The parameters W and L are a gate width and a gate length of the MOS transistor, respectively. The parameter μ is an average surface mobility, and Cox is a gate capacitance per unit area. Especially when the drain-source voltage Vd is small (for example, 1 V or less), the drain current Id is expressed by the following equation:
                              I          d                =                              W            L                    ⁢          μ          ⁢                                          ⁢                                    C              ox                        ⁡                          (                                                V                  g                                -                                  V                  t                                            )                                ⁢                      V            d                                              (        2        )            
FIG. 2 shows IV characteristics of the memory cell 110 and the dummy cell 120, in the nonvolatile semiconductor memory device 100. In FIG. 2, a vertical axis indicates the drain current Id, while a horizontal axis indicates a voltage Vcg applied to the control gate. Here, as shown in FIG. 1, sources of the memory cell 110 and the dummy cell 120 are connected to a ground. Therefore, the control gate voltage Vcg in FIGS. 1 and 2 can be considered to represent the gate-source voltage Vg mentioned above. The memory cell 110 in which electrons are injected into the floating gate is referred to as an “OFF memory cell” hereinafter. On the other hand, the memory cell 110 in which electrons are drawn out of the floating gate is referred to as an “ON memory cell” hereinafter. The ON memory cell corresponds to an erase memory cell from which the electrons are erased, and is related to a data value “0” for example. On the other hand, the OFF memory cell corresponds to a program memory cell, and is related to the data value “1” for example. The threshold voltages of the ON memory cell and the OFF memory cell are Vt0 and Vt1, respectively.
As expressed in the above equation (2) and shown in FIG. 2, the drain current Id is almost proportional to the control gate voltage Vcg (the gate-source voltage Vg) in the strong inversion region. A proportional coefficient (changing rate of the drain current Id to the change in the control gate voltage Vcg) of the dummy cell 120 is set to be smaller than that of the memory cell 110. It should be noted that the proportional coefficient can be adjusted by changing the gate capacitance Cox, the gate width W, and the gate length L. The threshold voltage Vtd of the dummy cell 120 is lower than the threshold voltage Vt0 of the ON memory cell, because potentials of the control gate and the floating gate of the dummy cell 120 are the same. Therefore, the IV characteristic of the dummy cell 120 is as indicated by a line in FIG. 2.
In a read operation, the same control gate voltage Vcg is applied to the control gates of the memory cell 110 and the dummy cell 120 having such IV characteristics. The voltage applied at the time of the read operation is referred to as a “read voltage VR” hereinafter. As shown in FIG. 2, the read voltage VR is set between the threshold voltages Vt0 and Vt1. Therefore, in the read operation, the ON memory cell operates in the strong inversion region and a drain current (a read current) Ion flows through the ON memory cell. Also, the dummy cell 120 operates in the strong inversion region and a drain current (a reference current) Iref flows through the dummy cell 120.
Here, the read voltage VR is lower than the threshold voltage Vt1 of the OFF memory cell. Therefore, the OFF memory cell does not operate in the strong inversion region. However, that's not to say that no electric current flows through the OFF memory cell at all. In an actual MOS transistor, a minute electric current flows when a potential difference exists between the source and the drain, even if the gate voltage is equal to or less than the threshold voltage. The cause is as follows: Some electrons exist near the surface of a substrate beneath the gate, though the electron density is not high. Therefore, a minute electric current can flow when the electrons mentioned above are carried in the substrate to the drain side due to diffusion. Such a state is referred to as an operation in a “weak inversion region”. The drain current Id of a general MOS transistor in the “weak inversion region” is expressed by the following equation:
                              I          d                =                              I            d            0                    ⁢          exp          ⁢                                                    qV                g                                                              mk                  B                                ⁢                T                                      ⁡                          [                              1                -                                  exp                  ⁡                                      (                                          -                                                                        qV                          d                                                                                                      k                            B                                                    ⁢                          T                                                                                      )                                                              ]                                                          (        3        )            
Here, q, kB, T and m are quantity of electric charge, the Boltzmann constant, an absolute temperature and a predetermined parameter, respectively. Also, Vg is a gate-source voltage (Vgs), and Vd is a drain-source voltage (Vds). As shown in FIG. 2, a small drain current Ioff flows through the OFF memory cell as well, when the read voltage VR is applied to the control gate. In the nonvolatile semiconductor memory device 100, whether a memory cell 110 is an ON memory cell or an OFF memory cell is sensed by comparing a current Icell (Ion, Ioff) from the memory cell 110 and the reference current Iref from the dummy cell 120.
Detailed configuration and operation of the nonvolatile semiconductor memory device 100 are as follows. As shown in FIG. 1, the current sense amplifier circuit 140 is provided with a PMOS 141, a PMOS 142, an NMOS 143, an NMOS 144 and an NOR 145. The PMOSs 141 and 142 constitute a current mirror circuit. The NOR 145 turns off the NMOS 143 in response to a stop signal Stop and thereby prevents electric currents from flowing when unnecessary. The reference current circuit 150 is provided with a PMOS 151, a PMOS 152, an NMOS 153, an NMOS 154 and an NOR 155. The PMOSs 151 and 152 constitute a current mirror circuit. The NMOSs 144 and 153 also constitute a current mirror circuit. The NOR 155 turns off the NMOS 154 in response to a stop signal Stop and thereby prevents electric currents from flowing when unnecessary. The PMOSs 141, 142, 151 and 152 have the same size. The NMOSs 143 and 154 have the same size. The NMOSs 144 and 153 have the same size. Also, transistors constituting the NORs 145 and 155 all have the same size.
In a read operation, the same read voltage VR is applied to the control gates of the memory cell 110 and the dummy cell 120. At this time, a memory cell current Icell (Ion, Ioff) flows through the memory cell 110 in accordance with a stored data. The memory cell current Icell also flows through the PMOS 141. Since the PMOSs 141 and 142 constitute the current mirror circuit and have the same transistor size, a current flowing through the PMOS 142 is also the memory cell current Icell.
On the other hand, the reference current Iref (e.g. 10 μA) flows through the dummy cell 120. At this time, the reference current Iref also flows through the PMOS 152. Since the PMOSs 151 and 152 constitute the current mirror circuit and have the same transistor size, the current flowing through the PMOS 151 is also the reference current Iref. Consequently, the reference current Iref also flows through the NMOS 153. Similarly, since the NMOSs 144 and 153 constitute the current mirror circuit and have the same transistor size, the current flowing through the NMOS 144 is also the reference current Iref. The current flowing through the NMOS 144 is used for sensing the data stored in the memory cell 110, and is referred to as a “sense current Isen” hereinafter.
In a case when the memory cell 110 is an ON memory cell (data value: 0), namely, when the memory cell current Icell is a read current Ion, as shown in FIG. 2, the read current Ion is larger than the sense current Isen (the reference current Iref). In this case, voltage at a connection point O1 in FIG. 1 is increased up to near a power supply voltage VDD. As a result, a logical value “Low” is output from an output OUT through an inverter 131 connected to the connection point O1. On the other hand, in a case when the memory cell 110 is an OFF memory cell (data value: 1), namely, when the memory cell current Icell is a read current Ioff, the read current Ioff is smaller than the sense current Isen (the reference current Iref), as shown in FIG. 2. In this case, voltage at the connection point O1 in FIG. 1 is decreased down to near a ground voltage GND, and a logical value “Hi” is output from the output OUT. As described above, when a relation “Ion>Iref>Ioff” is satisfied, the read operation is carried out normally.
The following techniques are also known as related arts.
Japanese Laid Open Patent Application JP-A-Heisei 09-320283 discloses a technique whose object is to match between a rise voltage (a gate voltage with which a current begins to flow) of a dummy cell and that of a memory cell. A nonvolatile semiconductor memory device described in the document has: a memory cell consisting of a stacked gate type NMOS; a dummy cell consisting of a single gate type NMOS; first and second capacitance elements; and a differential amplification sense amplifier. The first and second capacitance elements are connected in series between a power supply and a ground. A capacitance ratio between the first and second capacitance elements is approximately the same as that of the cell transistors. Potential at a connection point between the first and second capacitance elements is supplied to a gate of the dummy cell transistor. The differential amplification sense amplifier compares a read voltage from the memory cell side and a reference voltage from the dummy cell side.
Japanese Laid Open Patent Application JP-P2001-229686A discloses a technique whose object is to ensure a correct read operation even if temperature and manufacturing process conditions are changed. A nonvolatile semiconductor memory device described in the document has a memory cell transistor, a reference transistor, a differential sense amplifier, and a gate voltage generating circuit that generates a gate voltage of the reference transistor. The gate voltage generating circuit is provided with a dummy cell transistor having the same structure as the memory cell transistor; a current mirror for generating an electric current proportional to a drain current of the dummy cell transistor; and a transistor means for generating the gate voltage of the reference transistor based on the generated electric current.
Japanese Laid Open Patent Application JP-P2004-030754A discloses a technique whose object is to set a reference current value with a high precision and a short period of time. A nonvolatile semiconductor memory device described in the document is provided with a differential amplifier circuit and an external terminal. The differential amplifier circuit sets a drain-source voltage of a dummy cell to a first reference voltage which depends on a power supply voltage, and controls a gate potential of the dummy cell with a second reference voltage which does not depend on the change in the power supply voltage. A reference current flowing through the dummy cell in response to a read control signal is output from the external terminal. On the basis of the current value output from the external terminal, the second reference voltage is adjusted and thereby the value of the reference current is corrected.